Verilog HDL is an Hardware Description Language. Every device that we study in Digital Electronics, whose hardware is possible, can be described in a language (code). Every machine, that we come across in today's world can be studied by making its FSM (Finite State Machine).
Today with the help of simple FSM, we are going to see the verilog code for washing machine. I am considering only few states in this.(All features of washing machine are not covered here)
First of all, Let us see the FSM of a simple washing machine:
Here in this fsm, there are 4 states.
1. "idle" state: It is the state when the machine is doing nothing and is idle. In "idle" state, if power button is "on" then the state transition takes place from state "idle" to state "a" and the output is low. If power button is "off ", then the state remains in "idle".
2. "a" state: In state "a", if fill_water is 1(that is if the water gets filled) then the state moves to state "b" otherwise it remains in state "a".
3. "b" state: It is the wash state of the machine. In "b" state, if add_det = 1(that is if the detergent is added) then the state moves to state "c" otherwise remain at state "b".
4. "c" state: It is the rinse state of the machine. In "c" state, if the water is filled that is if fill_water = 1, then the process gets completed and the state returns back to its idle state and the output is 1. Otherwise it remains in state "c".
Here is the verilog code:
//Code:
module washing_machine(rst,clk,power,fill_water,add_det,out);
input rst,clk,power,fill_water,add_det;
output out;
reg out;
reg [3:0] count=0;
reg [1:0] state;
parameter idle=0,a=1,b=2,c=3;
always @(posedge clk) begin
if (rst==1) begin
state <= idle;
out <= 0;
end
else
case (state)
idle: if (power==1) begin
state <= a;
out <= 0;
end
else
begin
state <= idle;
out <= 0;
end
a: if (fill_water==1) begin
state <= b;
out <= 0;
end
else
begin
state <= a;
out <= 0;
end
b: if (add_det==1) begin
state <= c;
out <= 0;
end
else
begin
state <= b;
out <= 0;
end
c: if (fill_water==1) begin
state <= idle;
out <= 1;
end
else
begin
state <= c;
out <= 0;
end
endcase
end
endmodule
//Testbench:
module washmacTB;
reg rst,clk,power,fill_water,add_det;
wire out;
washing_machine wm(.rst(rst),.clk(clk),.power(power),.fill_water(fill_water),.add_det(add_det),.out(out));
initial begin
$monitor($time,"rst %b clk %b power %b fill_water %b add_det %b out %b",rst,clk,power,fill_water,add_det,out);
clk=0;
rst=1;
power=1;
fill_water=1;
add_det=0;
#5 rst=0;
#5 power=1;
#5 fill_water=1;
#5 add_det=1;
#5 power=1;
#5 fill_water=1;
#5 add_det=0;
#5 power=1;
#5 fill_water=0;
#5 add_det=1;
end
always #1 clk = ~clk;
endmodule
Output Waveform:
Thank You.
